1. Field of the Invention
The present invention is directed towards a systolic memory array (SMA) and more particularly to a systolic memory array (SMA) that enables the access of memory arrays that are subdivided into a plurality of banks and these banks may be accessed in a pipelined manner.
2. Background of the Related Art
One perennial goal among circuit and system designers is to improve memory bandwidth and access times. One way of achieving this goal, while simultaneously improving bandwidths and access times in memory devices, is to divide or compartmentalize an internal memory structure into a plurality of blocks that expand or increase the width of the data bus that accesses the memory structure.
Memory structures used in microprocessors and computing systems (e.g. a processor and memory) are growing rapidly in size and capability to accommodate the larger, proliferating new applications of increasing complexity and to improve processor performance. In general, systolic structures are used for mapping computations or processes into hardware structures and SMAs are used to map computations or processes into memory structures.
There is typically a direct relationship between a memory's capacity and its physical size, where a larger memory results in a larger physical size and a smaller memory results in a smaller physical size. This larger physical size increases the access time due to the inherent wiring delay present in longer wires and communication paths associated with the larger size. This makes accessing data and information stored in a memory structure within a short time or an otherwise acceptable time an increasingly difficult process.
Therefore, the various exemplary embodiments of the present invention address the disadvantages mentioned above and disclose a memory array that includes a plurality of multiple banks, which are adjustable in size (e.g. they can be made smaller or larger). These banks have shared address lines and are accessed in a pipelined fashion. After a certain latency or delay transpires, data stored in the banks at every clock cycle can be read out. Memory accesses to this memory array are sustainable for both reads and writes.
The various exemplary embodiments of the present invention permits memory arrays subdivided in banks to be accessed in a pipelined fashion. This approach achieves a much higher sustainable memory bandwidth and possibly a shorter average access time than what the individual banks provide if they were accessed with shared non-pipelined buses. This design also alleviates the problem of driving long global bit lines in larger memories. Read access of this type of pipelined memory will exhibit physical locality properties and have variable latency. Banks that are located closer to an access port will have shorter access time than banks that are located farther away. Additionally, systolic memories are easier to implement because of their modular designs and they are also more cost effective to produce because of this modular characteristic.